// i2c.vhd
//
//这是是能从一个外部NUM（AT24C02A）读数据到一个256x8的外部SRAM块的I2C主接口程序，
//当用于写NUM的外部逻辑寄存器存取时，SRAM就从外部源读数据并且把数据写到特定的I2C地址。
//----------------------------------------------------------------------
//
//               Copyright 2004 Actel corporation
//
//----------------------------------------------------------------------
//
// Version 1.2  06/04/04 J.Vorgert - working file
//
//----------------------------------------------------------------------

`timescale 1ns / 1ps

module i2c (Reset_n, CLK, INIT, IENB, IADDR, IDATA, ICLK, UPDT,
            UENB, UADDR, UDATA, SDI, SDO, SCK);

input Reset_n;  /* active low reset */
input CLK    ;  /* processor clock  */
output INIT   ;  /* high during init */
output IENB   ;  /* low to enable write */
output [7:0] IADDR  ;  /* init address */
output [7:0] IDATA  ;  /* init data */
output ICLK   ;  /* init clock */

input UPDT   ;  /* high to trigger mirror image update */
output UENB   ;  /* low to enable fifo */
input [7:0] UADDR; /* write address */
input [7:0] UDATA;  /* write data */

input SDI    ;  /* serial input */
output SDO    ; /* active low open-drain drive enable - data */
output SCK    ; /* active low open-drain drive enable - clock */

reg IENB;
reg INIT;
reg UENB;
reg BTCK;
wire STEN;    
reg  [3:0] CSTATE;  
reg  [3:0] BCNT  ; 
reg  [7:0] CCNT  ; 
reg DLY     ;
reg D2 ;
wire D2I;
wire NKI     ;
reg NACK    ;
wire WRI     ;
wire RDI     ;
reg [8:0] BYTE   ;
reg [8:0] SDATA  ;
wire LD_BYTE  ;
reg STSP     ;
wire CTL_VAL  ;

always @ (posedge CLK or negedge Reset_n)
begin
  if(Reset_n == 1'b0)
     BTCK <= 1'b0;
  else
     BTCK <= #1 !BTCK;

end

// INIT is set at power-up and cleared when the state machine
// reaches state 0101.

always @ (negedge Reset_n or posedge CLK)
begin
  if(Reset_n == 1'b0)
     INIT <= 1'b1;
  else if(CSTATE == 4'b0101)
        INIT <= #1 1'b0 ;
end

// This state machine is set-up to read/write data to an AT24C02A
// serial Flash memory

//这个状态机是建立AT24C02A串行闪存" title="串行闪存">串行闪存的数据读写

// At power-up, the INIT bit is set, and the state machine executes
// a 'sequencial read' operation starting at address 0x000 and
// procedding until all 256 bytes have been read and forwarded into
// the internal memory block. The state machine then sends a
// stop bit to the Flash and clears the INIT control bit.
//
//在上电" title="上电">上电时，INIT被设置为高，状态机从地址0x000开始执行“连续读”操作，
//一直进行下去直到所有的256字节都被读，然后向前到内部存储区，
//状态机然后给FLASH发送一个停止位并且清除INIT控制位。

// The state machine then waits for updt to be set.
// When the updt bit is set, the interface asserts u_enb low on a
// falling-edge of clk and addr/data is latched  on the next falling edge
// (rd_clk should be on the rising-edge).  The state machine writes
// data to the external FLASH memory one byte at a time whenever
// updt is asserted high.  If the FIFO remains 'not empty' then this
// block will poll the NVM until it is ready, and then proceed with
// a write cycle for the next byte.

//状态机一直等待UPDT被置为高。当updt比特被置成高，当clk下降沿时，接口把u_enb设成低
//（rd_clk应该在上升沿）。这个状态机每次updt为高时就写一个字节数据到外部闪存。
//如果FIFO保持“非空”，则这个块会一直等到它准备好，然后在接下来的比特进行一个写周期。

// State Machine:
//
// 0000 - reset state:   generate a start bit and load 0xA0 command
// 0001 - send byte:     then load 0x00 address
// 0010 - send byte:     generate a start bit and load 0xA1 command
// 0011 - send byte:     clear byte count
// 0100 - receive byte:  if cnt /= FF: ack, cnt++, goto 0004 else: nack
// 0101 - stop:          assert stop bit and loop until updt = 1 - then
//                       generate a start bit and load A0
// 0110 - send byte:     send byte - if nack - goto 0101, else load Address
// 0111 - send byte:     send data byte, load data
// 1000 - send byte:     goto 0101
//
// In practice, the state machine is just a counter that starts at zero
// and counts up, then jumps back to 101 and counts up again,
// returning to zero only when reset_n is asserted low.
//在练习中，状态机只是一个从0开始计数的计数器，加起来，然后跳到101，再重新计数，
//只有到reset_n被置为低时才返回到0。

assign STEN = ( BCNT[3] == 1'b1 &&
                  (CSTATE[2] != 1'b1 || CSTATE[2:1] == 2'b11 ||
                   CSTATE[3]  == 1'b1 || (CSTATE == 4'b0100 && CCNT == 8'b11111111) ||
                  (CSTATE == 4'b0101 && UPDT == 1'b1)))?1'b1:1'b0;

always @(negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0) 
     CSTATE <= 4'b0000;
  else
  begin
  if(STEN == 1'b1 && BTCK == 1'b0)
        begin
         if(CSTATE < 4'b0101 && NACK == 1'b1)
           CSTATE <= #1 4'b0000 ;
        end
   else
        begin
        if (CSTATE[3] == 1'b1 || NACK == 1'b1)
          CSTATE <= #1 4'b0101 ;
        else
          CSTATE <= #1 CSTATE + 1'b1 ;
        end
  end
end

// The bit counter (BCNT) is cleared at the state transition
// and during the first cycle of state '0011' (for start bit).
// incremented on the falling-edge of clk when BTCK is low.

//比特计数器在过渡状态时和在状态“0011”（起始比特）第一个" title="第一个">第一个循环期间被清空。
//在clk下降沿并且BTCK为低电平时，比特计数器增加。

always @ (negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0)
     begin
     BCNT <= 4'b0000;
     DLY  <= 1'b0;
     end
  else
    begin
     if(BTCK == 1'b0)
       begin
       if(BCNT[3] == 1'b1 && CSTATE == 4'b0010)
          DLY <= #1 1'b1;
       else
          DLY <= 1'b0;
      
       if(BCNT[3] == 1'b1 || (CSTATE == 4'b0011 && DLY == 1'b1))
          BCNT <= #1 4'b0000;
       else
          BCNT <= #1 BCNT + 1'b1;
       end
   
    end
end

// The byte counter (CCNT) is cleared in state 0011.
//字节计数器在状态0011时被清零。

// It is incremented during the ACK bit after each
// byte transfer in state 0100 to count 0x00-0xFF bytes
// as they are read from the NVM.  ccnt is used both as
// a control signal and as the iaddr output.

assign D2I = (BTCK == 1'b1 && BCNT[3] == 1'b1 && CSTATE == 4'b0100)?1'b1:1'b0;
          

always @ (negedge Reset_n or negedge CLK)
begin
  if(Reset_n == 1'b0)
   begin
     CCNT <= 8'b0;
     D2   <= 1'b0;
   end
  else
   begin
     D2 <= #1 D2I;
     if(CSTATE == 4'b0011)
        CCNT <= #1 8'b0;
     else if(D2 == 1'b1)
        CCNT <= #1 CCNT + 1'b1;
     end
end

// the following logic checks the ACK bit for all states except
// states '0100' and '0101' and asserts NACK if the data pin is
// high during the 9th bit of any transfer.  This is registered
// so that the value is present during state changes.

            
endmodule