NXP公司的LPC4350/30/20/10是集成了多达264KB SRAM,以太网,两个高速USB控制器,LCD,外接存储器控制器,多个数字与模拟外设以及先进的可配置外设的32位ARM Cortex-M4/M0 MCU. 可配置外设包括状态可可配置定时器(SCT),串行通用I/O(SGPIO)接口.CPU工作频率高达204MHz,主要用在马达控制,工业自动化,电源管理,嵌入式音频应用, 电表,RFID阅读器和白色家电.本文介绍了LPC4350/30/20/10主要特性和优势,方框图以及Hitex LPC1850/4350评估板主要特性,方框图,电路图和PCB元件布局图.

LPC4350/30/20/10:32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet; two High-speed USBs; advanced configurable peripherals

The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM Cortex-M0 coprocessor, up to 264 kB of SRAM, advanced configurable peripherals such as the State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. The LPC4350/30/20/10 operate at CPU frequencies of up to 204 MHz.

The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated in the core.

The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor, designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz performance with a simple instruction set and reduced code size.

LPC4350/30/20/10主要特性和优势:

 Cortex-M4 Processor core

 ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.

 ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.

 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

 Hardware floating-point unit.

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 Cortex-M0 Processor core

 ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4 application processor.

 Running at frequencies of up to 204 MHz.

 JTAG, Serial Wire Debug, and built-in NVIC.

 On-chip memory

 Up to 264 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.

 64 kB ROM containing boot code and on-chip software drivers.

 128 bit general-purpose One-Time Programmable (OTP) memory.

 Configurable digital peripherals

 Serial GPIO (SGPIO) interface.

 State Configurable Timer (SCT) subsystem on AHB.

 Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCT, and ADC0/1.

 Serial interfaces

 Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second.

 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).

 One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY.

 One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.

 USB interface electrical test software included in ROM USB stack.

 One 550 UART with DMA support and full modem interface.

 Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface.

 Two C_CAN 2.0B controllers with one channel each.

 Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.

 One SPI controller.

 One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.

 One standard I2C-bus interface with monitor mode and with standard I/O pins.

 Two I2S interfaces, each with DMA support and with one input and one output.

 Digital peripherals

 External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices.

 LCD controller with DMA support and a programmable display resolution of up to 1024 H 768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping.

 Secure Digital Input Output (SD/MMC) card interface.

 Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB slaves.

 Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open-drain mode.

 GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.

 Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.

 Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.

 Four general-purpose timer/counters with capture and match capabilities.

 One motor control Pulse Width Modulator (PWM) for three-phase motor control.

 One Quadrature Encoder Interface (QEI).

 Repetitive Interrupt timer (RI timer).

 Windowed watchdog timer (WWDT).

 Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.

 Alarm timer; can be battery powered.

 Analog peripherals

 One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

 Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. ADC inputs are shared between the two ADCs.

 Security

 AES engine programmable through an on-chip API.

 Two 128-bit secure OTP memories for AES key storage and customer use.

 Unique ID for each device.

 Clock generation unit

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and voltage.

 Ultra-low power Real-Time Clock (RTC) crystal oscillator.

 Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.

 Clock output.

 Power

 Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the core supply and the RTC power domain.

 RTC power domain can be powered separately by a 3 V battery supply.

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.

 Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.

 Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.

 Brownout detect with four separate thresholds for interrupt and forced reset.

 Power-On Reset (POR).

 Available as 256-pin, 180-pin, and 100-pin LBGA package and as 208-pin, 144-pin. and 100-pin LQFP packages.

LPC4350/30/20/10主要应用:

Motor control 

Embedded audio applications

Power management 

Industrial automation

White goods 

e-metering

RFID readers

图1.LPC4350/30/20/10方框图

Hitex LPC1850/4350评估板

Simultaneously with the introduction of NXP’s LPC1800/4350 microcontrollers Hitex introduces the LPC1850 and LPC4350 evaluation board with some special features. The board is USB-powered, but can also be driven by external power supply or via power-over-Ethernet. It is equipped with 65MB SDRAM, 32MB parallel flash and 512kB SRAM and a serial EEPROM. For debugging a JTAG as well as a 20-pin Cortex debug connector with ETM is available. All channels (USB1 and USB2) as well as Ethernet are provided by Phy. This makes USB device, USB host and OTG available as well as UART and CAN.


图2.Hitex LPC1850/4350评估板方框图

The Hitex LPC4350 Eval board allows you to quickly and easily evaluate the LPC4300 family of microcontrollers. The microcontroller, board, and the accompanying features make it a great starting point for your next Cortex-M4 project.

Populated with the LPC4350 to demonstrate LPC4300 features, the LPC4350 offers industry leading dual-core performance, large internal memories and advanced peripherals.

图3.Hitex LPC1850/4350评估板外形图

Note: Same as Hitex LPC1850 Evaluation Board, but with LPC4350 component replacing LPC1850.

Hitex LPC1850/4350评估板主要特性:

- CPU: LPC1850 /4350(ARM Cortex-M3)

- Power-over-Ethernet

- Ready for energy consumption analysis with PowerScale of the complete board, the CPU-core and other peripherals

- SDRAM, SRAM, parallel flash, NAND flash, qSPI flash

- Temperature sensor, SD card, media-connector

- CAN, UART, Ethernet, USB (Host, Device, OTG)

- Debug with standard ARM JTAG and JTAG + Trace connector

- Ready for Jennic ZigBee module

- Small onboard display and NXP standard display / LCD interface

- Touch buttons and LEDs

- Wrap field for user circuits

- Audio IN and OUT, microphone IN, headphones OUT and a D-Class amplifier

- Ready for 4x ADC1415 analog-to-digital converters with user filtering option

图4.Hitex LPC1850评估板电路图(1)

图5.Hitex LPC1850评估板电路图(2)

图6.Hitex LPC1850评估板电路图(3)

图7.Hitex LPC1850评估板电路图(4)

图8.Hitex LPC1850评估板电路图(5)


图9.Hitex LPC1850评估板电路图(6)

图10.Hitex LPC1850评估板电路图(7)

图11.Hitex LPC1850评估板PCB元件布局图
详情请见:
http://www.nxp.com/documents/data_sheet/LPC4350_30_20_10.pdf
和
http://www.nxp.com/documents/other/Hitex_LPC1850_Eval_Board_UserManual.pdf
以及
http://www.hitex-download.de/lpc/lpc1800/SCM_LPC1850EVA-A2-2.pdf