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5 nm MSOA RapidPDK及物理实现
2021年电子技术应用第8期
贺恺华1,丁学伟1,2
1.深圳市中兴微电子技术有限公司IP设计部,广东 深圳518055; 2.移动网络和移动多媒体技术国家重点实验室,广东 深圳518055
摘要: 随着当今电子行业的发展,对SoC芯片,尤其是数模混合芯片的要求越来越高。和传统的DEF/GDS数据交互方式相比,Mixed Signal Open Database(MSOA) RapidPDK可以帮助设计人员通过相同的PDK更好地完成数字工具Innovus和模拟工具Virtuoso之间的数据传递。首先描述了5 nm MSOA RapidPDK生成方式,其次使用生成的PDK实现5 nm IP物理实现,同时验证MSOA flow对5 nm设计在版图完成和交付方面的速率提升。
中图分类号: TN402
文献标识码: A
DOI:10.16157/j.issn.0258-7998.219805
中文引用格式: 贺恺华,丁学伟. 5 nm MSOA RapidPDK及物理实现[J].电子技术应用,2021,47(8):59-63,67.
英文引用格式: He Kaihua,Ding Xuewei. 5 nm physical implementation with MSOA RapidPDK[J]. Application of Electronic Technique,2021,47(8):59-63,67.
5 nm physical implementation with MSOA RapidPDK
He Kaihua1,Ding Xuewei1,2
1.IP Design Department of Sanechips Technology Co.,Ltd.,Shenzhen 518055,China; 2.State Key Laboratory of Mobile Network and Mobile Multimedia Technology,Shenzhen 518055,China
Abstract: Success in today′s electronics market place,most SoCs currently being developed have analog or mixed signal blocks, many so-called analog blocks actually have digital-control logic.Virtuoso-innovus flow with MSOA RapidPDK allows for all or parts of the physical hierarchy to pass back and forth between Virtuoso and Innovus easily without having to generate a DEF/GDS file. In this paper, we firstly describe the way to generate 5 nm RapidPDK, then use this PDK with digital flow to finish 5 nm IP design with custom lib. Additionally, this Virtuoso-innovus flow provides our analog designers with advanced techniques for 5 nm floorplanning, pin optimization, track generation and auto place & routing with RC extraction and timing analysis aware which will simplify the flow to enable virtuoso users to run 5 nm layout implementation, and also could help us to do full chip STA analysis
Key words : MSOA RapidPDK;5 nm;Virtuoso;Innovus

0 引言

    随着芯片工艺的发展,数模混合芯片中的数字和模拟模块(Block)已经没有明显的区分界限,很多情况下,模拟模块的内部会包含数字模块,随之而来的问题是需要大量时间和精力解决在数字和模拟模块之间数据交互的问题和彼此database的兼容性。同时先进工艺下随着double pattern等特性的引入,模拟版图的实现变得更加复杂,而如何提高效率,保证数据准确性也变得更加重要。



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作者信息:

贺恺华1,丁学伟1,2

(1.深圳市中兴微电子技术有限公司IP设计部,广东 深圳518055;

2.移动网络和移动多媒体技术国家重点实验室,广东 深圳518055)




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