中图分类号：TN710 文献标志码：A DOI: 10.16157/j.issn.0258-7998.257193
中文引用格式： 林晓会，陈宇轩，宋国栋，等. 互连线延迟对测试时间的影响研究[J]. 电子技术应用，2026，52(4)：49-53.
英文引用格式： Lin Xiaohui，Chen Yuxuan，Song Guodong，et al. Research on the impact of interconnect delay on test time[J]. Application of Electronic Technique，2026，52(4)：49-53.

Research on the impact of interconnect delay on test time

Abstract： In the mass production testing of FPGA devices, the internal interconnection resources consume a significant amount of testing time. How to reduce testing time and save testing costs has been a major challenge for mass production. To address this issue, taking the XCKU5P FPGA as a verification example, we used Vivado to perform timing simulation on the tested interconnection paths, and based on the actual measurements from the ATE, we obtained the transmission delay of the interconnection lines, which was consistent with the simulation results. Furthermore, we studied the interconnection line delay under different test temperatures and identified the reasonable and stable delay wait time for ATE testing of FPGA interconnection functions. Through validation, adding 100 ns to the minimum delay wait time required for low-temperature functional testing can meet the stability requirements of three-temperature testing, effectively reducing the unnecessary redundant wait time set based on experience, thus improving testing efficiency and reducing testing costs.

Key words : interconnect line；FPGA；transmission delay；automatic test equipment；test optimization