中图分类号：TN402；TP338.8 文献标志码：A DOI: 10.16157/j.issn.0258-7998.257651
中文引用格式： 冯烁，路冬冬，尹飞，等. 基于空间访存规律的数据和页表联合硬件预取设计[J]. 电子技术应用，2026，52(10)：155-163.
英文引用格式： Feng Shuo，Lu Dongdong，Yin Fei，et al. A joint hardware prefetching design of data cache and page tables based on spatial memory correlations[J]. Application of Electronic Technique，2026，52(10)：155-163.

A joint hardware prefetching design of data cache and page tables based on spatial memory correlations

Abstract： The development of modern high-performance processors is making remarkable progress on a daily basis, while the technical challenges and problems resided in CPU architectures or microarchitectures faced by chip designers are also getting severer than ever. For example, the cost of main memory access is raising dramatically, and the latency for address translation is overwhelming, which would inevitably affect the overall performance of program executions for high-performance processors. Among others, hardware prefetching is an effective method to improve the ratio of data cache hit, resulting in a much narrowed and tolerable memory access latency. In this paper, an introduction on the pattern-based data prefetching and execution-based data prefetching is given firstly, a brief analysis on the temporal, spatial, and pointer-detection prefetching is provided, a thorough discussion is dedicated to the methods of delta prefetching and footprint prefetching, and the comparison of design details between a few representative spatial data prefetchers is summarized. Moreover, this paper proposes a joint hardware prefetching design of data cache and page tables, whose key idea is to fully exploit the spatial memory correlations of page tables, and implement the data prefetching based on the page-table prefetching, for the purpose of further improving the performance of existing spatial data prefetching methods.

Key words : CPU architecture；microarchitecture design；hardware data prefetching；address translation；spatial memory correlations