中图分类号：TP302文献标识码：ADOI:10.19339/j.issn.1674-2583.2026.010.003
中文引用格式：黄旭东，田亚南，洪泽. 基于GEM5的RISCV乱序内核微架构参数优化研究［J］.集成电路应用，2026，43（10）：14-18.
英文引用格式：Huang Xudong，Tian Yanan，Hong Ze. Research on microarchitecture parameter optimization of a RISCV outoforder core based on GEM5［J］.Application of IC，2026，43（10）：14-18.

esearch on microarchitecture parameter optimization of a RISC-V out-of-order core based on GEM5

Abstract： This study optimizes microarchitecture parameters for an out-of-order RISC-V superscalar processor in embedded scenarios. A simulation model was built on GEM5 v25.1 with the RiscvO3CPU core, using CoreMark, Dhrystone, Whetstone, and Embench (crc32, matmult-int) as embedded benchmarks, and cross-validated with SPEC CPU2006 (mcf, bzip2_ref). The effects of issue width, reorder buffer (ROB), load/store queue (LQ/SQ), physical register file, and functional units on performance and energy efficiency were systematically investigated. Experimental results showed that embedded workloads were highly sensitive to functional unit configuration: reducing integer ALUs from 2 to 1, while degrading CoreMark IPC by 37.5%. An issue width of 3 already saturated CoreMark performance. Saturation points for ROB size, LQ/SQ depth, and physical register file were 64 entries, 32/32 entries, and 96/96 entries, respectively. Power and energy efficiency were evaluated using the McPAT 22 nm process model. EDP analysis indicates that the baseline configuration achieves the best energy-efficiency trade-off for embedded applications.

Key words : RISC-V; out-of-order core; GEM5; microarchitecture parameter optimization