A Time Scaling Theory for Multi-Layer Electronic SystemsAET-电子技术应用-最丰富的电子设计资源平台

A Time Scaling Theory for Multi-Layer Electronic Systems
所属分类：解决方案
上传者：wwei
文档大小：533 K
标签： Time Scaling τ scaling LogicFolding
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文档介绍： For six decades, Moore's geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling. This perspective argues for a successor scaling principle — τ scaling —that adopts time itself, rather than transistor area, as the primary metric of progress, applying a single characteristic time constant τ as the unifying optimization target across twelve orders of magnitude, from a switching transistor to a data-center workload. Two production-scale demonstrations are presented. On a mobile SoC, LogicFolding — a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers — delivers a 55% step-wise increase in transistor density and a 41% power-efficiency gain at a fixed device node.……
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