中图分类号：TN402 文献标志码：A DOI: 10.16157/j.issn.0258-7998.260801
中文引用格式： 陆晶晶，孙琳杰，刘宇朝. Smart ECO 在关键block上的评估和应用[J]. 电子技术应用，2026，52(8)：40-43.
英文引用格式： Lu Jingjing，Sun Linjie，Liu Yuzhao. Evaluation and application of Smart ECO on key blocks[J]. Application of Electronic Technique，2026，52(8)：40-43.

Evaluation and application of Smart ECO on key blocks

Abstract： Before and after chip tape-out, local modifications are usually required through Engineering Change Order (ECO) to fix design defects or performance issues, while minimizing the impact on the overall design. Currently, the Conformal platform is the mainstream solution for this purpose. However, for critical modules, its FEF flow tends to generate large ECO patch size with high resource consumption, bringing significant challenges to subsequent physical integration, such as layout routing closure and timing convergence. After evaluation and practical verification on multiple ECO flows, the Smart ECO flow has demonstrated significant advantages in terms of ECO patch size reduction and runtime efficiency. It effectively reduces resource occupation, thereby significantly improving the efficiency of backend layout routing and the success rate of timing verification, providing strong support for chip design optimization.

Key words : Smart ECO；patch size；runtime